On Sat, Aug 6, 2016 at 3:47 PM, Richard Henderson wrote:
> On 08/02/2016 03:50 PM, vijay.kil...@gmail.com wrote:
>>
>> +#define VEC_PREFETCH(base, index) \
>> +asm volatile ("prfm pldl1strm, [%x[a]]\n" : :
>> [a]"r"(&base[(index)]))
>
>
> Is this not __builtin_prefetch(base + index) ?
>
>
On 08/12/2016 12:32 PM, Vijay Kilari wrote:
On Sat, Aug 6, 2016 at 3:47 PM, Richard Henderson wrote:
On 08/02/2016 03:50 PM, vijay.kil...@gmail.com wrote:
+#define VEC_PREFETCH(base, index) \
+asm volatile ("prfm pldl1strm, [%x[a]]\n" : :
[a]"r"(&base[(index)]))
Is this not __built
On 08/02/2016 03:50 PM, vijay.kil...@gmail.com wrote:
+#define VEC_PREFETCH(base, index) \
+asm volatile ("prfm pldl1strm, [%x[a]]\n" : : [a]"r"(&base[(index)]))
Is this not __builtin_prefetch(base + index) ?
I.e. you can defined this generically for all targets.
+#if defined (__aarc
From: Vijaya Kumar K
Thunderx pass2 chip requires explicit prefetch
instruction to give prefetch hint.
To speed up live migration on Thunderx platform,
prefetch instruction is added in zero buffer check
function.
The below results show live migration time improvement
with prefetch instruction w
