Peter Maydell writes:
> On 10 July 2017 at 13:15, Alex Bennée wrote:
>> Looking at translate.c (32 bit arm), we have:
>>
>> gen_srs
>> gen_mrs_banked
>> gen_msr_banked
>>
>> These all manually set:
>>
>> gen_set_pc_im(s, s->pc - 4);
>>
>> before their respective helpers. I think setting
On 10 July 2017 at 13:15, Alex Bennée wrote:
> Looking at translate.c (32 bit arm), we have:
>
> gen_srs
> gen_mrs_banked
> gen_msr_banked
>
> These all manually set:
>
> gen_set_pc_im(s, s->pc - 4);
>
> before their respective helpers. I think setting the PC after the helper
> is superflu
Richard Henderson writes:
> On 07/07/2017 08:29 AM, Alex Bennée wrote:
>>> Naming all of these different exit conditions is certainly
>>> non-trivial.
>>
>> Given the variation of usage this is something that should probably be
>> done after Lluís common run loop goes in and we can beef up the
>
On 07/07/2017 08:29 AM, Alex Bennée wrote:
Naming all of these different exit conditions is certainly
non-trivial.
Given the variation of usage this is something that should probably be
done after Lluís common run loop goes in and we can beef up the
semantics of the various exit conditions.
D
On 07/07/2017 07:36 AM, Peter Maydell wrote:
On 7 July 2017 at 18:32, Alex Bennée wrote:
Given the wording of:
/* is_jmp field values */
#define DISAS_NEXT0 /* next instruction can be analyzed */
#define DISAS_JUMP1 /* only pc was modified dynamically */
#define DISAS_UPDATE 2 /* cpu
On 7 July 2017 at 18:32, Alex Bennée wrote:
> Given the wording of:
>
> /* is_jmp field values */
> #define DISAS_NEXT0 /* next instruction can be analyzed */
> #define DISAS_JUMP1 /* only pc was modified dynamically */
> #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
> #
Richard Henderson writes:
> On 07/07/2017 07:36 AM, Peter Maydell wrote:
>> On 7 July 2017 at 18:32, Alex Bennée wrote:
>>> Given the wording of:
>>>
>>> /* is_jmp field values */
>>> #define DISAS_NEXT0 /* next instruction can be analyzed */
>>> #define DISAS_JUMP1 /* only pc was modif
Alex Bennée writes:
> Previously DISAS_JUMP did ensure this but with the optimisation of
> 8a6b28c7 (optimize indirect branches) we might not leave the loop.
> This means if any pending interrupts are cleared by changing IRQ flags
> we might never get around to servicing them. You usually notice
Previously DISAS_JUMP did ensure this but with the optimisation of
8a6b28c7 (optimize indirect branches) we might not leave the loop.
This means if any pending interrupts are cleared by changing IRQ flags
we might never get around to servicing them. You usually notice this
by seeing the lookup_tb_p
