Re: [Qemu-devel] [RFC 12/28] target-xtensa: implement shifts (ST1 and RST1 groups)

2011-05-05 Thread Max Filippov
>> To track immediate values written to SAR? You mean that there may be >> some performance difference of fixed size shift vs indirect shift and >> TCG is able to tell them apart? > > Well, not really fixed vs indirect, but if you know that the value > in the SAR register is in the right range, you

Re: [Qemu-devel] [RFC 12/28] target-xtensa: implement shifts (ST1 and RST1 groups)

2011-05-04 Thread Richard Henderson
On 05/04/2011 09:39 AM, Max Filippov wrote: > To track immediate values written to SAR? You mean that there may be > some performance difference of fixed size shift vs indirect shift and > TCG is able to tell them apart? Well, not really fixed vs indirect, but if you know that the value in the SAR

Re: [Qemu-devel] [RFC 12/28] target-xtensa: implement shifts (ST1 and RST1 groups)

2011-05-04 Thread Max Filippov
>> +                    HAS_OPTION(XTENSA_OPTION_MISC_OP); >> +                    { >> +#define gen_bit_bisect(w) do { \ >> +        int label = gen_new_label(); \ >> +        tcg_gen_brcondi_i32(TCG_COND_LTU, tmp, 1 << (w), label); \ >> +        tcg_gen_shri_i32(tmp, tmp, (w)); \ >> +        tcg_

Re: [Qemu-devel] [RFC 12/28] target-xtensa: implement shifts (ST1 and RST1 groups)

2011-05-04 Thread Richard Henderson
On 05/03/2011 05:59 PM, Max Filippov wrote: > +HAS_OPTION(XTENSA_OPTION_MISC_OP); > +{ > +#define gen_bit_bisect(w) do { \ > +int label = gen_new_label(); \ > +tcg_gen_brcondi_i32(TCG_COND_LTU, tmp, 1 << (w), label); \ > +tcg_gen_shri_

[Qemu-devel] [RFC 12/28] target-xtensa: implement shifts (ST1 and RST1 groups)

2011-05-03 Thread Max Filippov
- ST1: SAR (shift amount special register) manipulation, NSA(U); - RST1: shifts, 16-bit multiplication. Signed-off-by: Max Filippov --- target-xtensa/cpu.h |4 + target-xtensa/translate.c | 210 + 2 files changed, 214 insertions(+), 0 deleti