On Wed, 2017-05-24 at 02:15 -0300, Philippe Mathieu-Daudé wrote:
> Hi Andrew,
>
> On 05/22/2017 02:14 AM, Andrew Jeffery wrote:
> > On Mon, 2017-05-22 at 03:15 +, Ryan Chen wrote:
> > > In ASPEED SoC chip, all register access have following rule.
> > > Most of controller write access is only s
Hi Andrew,
On 05/22/2017 02:14 AM, Andrew Jeffery wrote:
On Mon, 2017-05-22 at 03:15 +, Ryan Chen wrote:
In ASPEED SoC chip, all register access have following rule.
Most of controller write access is only support 32bit access.
Read is support 8bits/16bits/32bits.
This makes sens thinking
In ASPEED SoC chip, all register access have following rule.
Most of controller write access is only support 32bit access.
Read is support 8bits/16bits/32bits.
Best Regards,
Ryan
信驊科技股份有限公司
ASPEED Technology Inc.
2F,No.15,Industry East Road 4.,Hsinchu Science Park, Hsinchu City 30077, Taiwan
On Mon, 2017-05-22 at 03:15 +, Ryan Chen wrote:
> In ASPEED SoC chip, all register access have following rule.
> Most of controller write access is only support 32bit access.
> Read is support 8bits/16bits/32bits.
Thanks for clearing that up Ryan.
Phil: I'll rework the model so the reads a
Hi Phil,
On Sat, 2017-05-20 at 00:21 -0300, Philippe Mathieu-Daudé wrote:
> Hi Andrew,
>
> On 05/19/2017 09:26 PM, Andrew Jeffery wrote:
> > This model implements enough behaviour to do basic functionality tests
> > such as device initialisation and read out of dummy sample values. The
> > sample
Hi Andrew,
On 05/19/2017 09:26 PM, Andrew Jeffery wrote:
This model implements enough behaviour to do basic functionality tests
such as device initialisation and read out of dummy sample values. The
sample value generation strategy is similar to the STM ADC already in
the tree.
Signed-off-by: A
