Re: [Qemu-devel] [PATCH v8 01/27] target-arm: extend async excp masking

2014-11-05 Thread Greg Bellows
Actually it is possible to make it simpler and avoid the gotos altogether with the changes I have made using the following conditional: +/* Use the target EL, current execution state and SCR/HCR settings to + * determine whether the corresponding CPSR bit is used to mask the + * interr

Re: [Qemu-devel] [PATCH v8 01/27] target-arm: extend async excp masking

2014-10-31 Thread Peter Maydell
On 30 October 2014 21:28, Greg Bellows wrote: > This patch extends arm_excp_unmasked() to use lookup tables for determining > whether IRQ and FIQ exceptions are masked. The lookup tables are based on the > ARMv8 and ARMv7 specification physical interrupt masking tables. > > If EL3 is using AArch6

[Qemu-devel] [PATCH v8 01/27] target-arm: extend async excp masking

2014-10-31 Thread Greg Bellows
This patch extends arm_excp_unmasked() to use lookup tables for determining whether IRQ and FIQ exceptions are masked. The lookup tables are based on the ARMv8 and ARMv7 specification physical interrupt masking tables. If EL3 is using AArch64 IRQ/FIQ masking is ignored in all exception levels oth