Re: [Qemu-devel] [PATCH v7 2/6] Implement GIC-500 base class

2015-08-03 Thread Pavel Fedin
Hello! > For this patch series we should retain this class hierarchy, > but remove all the fields corresponding to state information > which isn't used by the KVM subclass (and all the accessor > macro definitions, and that GICV3_NCPU definition, and so on). > We should have a migration informati

Re: [Qemu-devel] [PATCH v7 2/6] Implement GIC-500 base class

2015-07-31 Thread Peter Maydell
On 26 July 2015 at 14:52, Pavel Fedin wrote: > And could you be not so strict on this file? OK, so having thought about this this week, this is what I suggest. For this patch series we should retain this class hierarchy, but remove all the fields corresponding to state information which isn't u

Re: [Qemu-devel] [PATCH v7 2/6] Implement GIC-500 base class

2015-07-26 Thread Peter Maydell
On 26 July 2015 at 14:52, Pavel Fedin wrote: >> This whole struct reads like "we just took the GICv2 state >> and changed it as little as possible beyond bumping the >> NCPU define a bit". That doesn't make me very confident >> that it's actually correct for GICv3... > > At least, with complete

Re: [Qemu-devel] [PATCH v7 2/6] Implement GIC-500 base class

2015-07-26 Thread Shlomo Pongratz
Hi, See inline. On Friday, July 24, 2015, Peter Maydell wrote: > On 24 July 2015 at 10:55, Pavel Fedin > > wrote: > > From: Shlomo Pongratz > > > > > This class is to be used by both software and KVM implementations of > GICv3 > > > > > +++ b/include/hw/intc/arm_gicv3_common.h > > @@ -0,0 +1,11

Re: [Qemu-devel] [PATCH v7 2/6] Implement GIC-500 base class

2015-07-26 Thread Pavel Fedin
Hello! > > + > > +typedef struct gicv3_irq_state { > > +/* The enable bits are only banked for per-cpu interrupts. */ > > +uint64_t enabled; > > +uint64_t pending; > > +uint64_t active; > > +uint64_t level; > > +uint64_t group; > > Why are these uint64_t ? I studied th

Re: [Qemu-devel] [PATCH v7 2/6] Implement GIC-500 base class

2015-07-26 Thread Pavel Fedin
Hello! > So how do LPIs work? They have IDs above 1023. Currently we don't have LPIs. Shlomo's SW emulation did not include them. > > +#define GICV3_NCPU 64 > > Where does '64' come from as a maximum limit? We don't use Aff2 field as far as i know. It's Shlomo's limitation, not my one. > T

Re: [Qemu-devel] [PATCH v7 2/6] Implement GIC-500 base class

2015-07-24 Thread Peter Maydell
On 24 July 2015 at 10:55, Pavel Fedin wrote: > From: Shlomo Pongratz > > This class is to be used by both software and KVM implementations of GICv3 > > +++ b/include/hw/intc/arm_gicv3_common.h > @@ -0,0 +1,112 @@ > +/* > + * ARM GIC support > + * > + * Copyright (c) 2012 Linaro Limited > + * Cop

[Qemu-devel] [PATCH v7 2/6] Implement GIC-500 base class

2015-07-24 Thread Pavel Fedin
From: Shlomo Pongratz This class is to be used by both software and KVM implementations of GICv3 Signed-off-by: Shlomo Pongratz Signed-off-by: Pavel Fedin --- hw/intc/Makefile.objs | 1 + hw/intc/arm_gicv3_common.c | 249 + hw/intc/gi