On Fri, Apr 11, 2014 at 2:15 AM, Peter Maydell wrote:
> Implement AArch64 view of the CONTEXTIDR register.
> We tighten up the condition when we flush the TLB on a CONTEXTIDR
> write to avoid needlessly flushing the TLB every time on a 64
> bit system (and also on a 32 bit system using LPAE, as a
Implement AArch64 view of the CONTEXTIDR register.
We tighten up the condition when we flush the TLB on a CONTEXTIDR
write to avoid needlessly flushing the TLB every time on a 64
bit system (and also on a 32 bit system using LPAE, as a bonus).
Signed-off-by: Peter Maydell
---
target-arm/cpu.h
