On 01/04/2012 11:50 AM, Peter Maydell wrote:
> On 4 January 2012 16:53, Mark Langsdorf wrote:
>> +} else if ((op1 == 0) && (op2 == 0)) {
>> +/* power_control should be set to maximum latency. Again,
>> + default to 0 and set by private hook */
>> +
On 4 January 2012 16:53, Mark Langsdorf wrote:
> + if (ARM_CPUID(env) == ARM_CPUID_CORTEXA9) {
> + switch (crm) {
> + case 0:
> + if ((op1 == 4) && (op2 == 0)) {
> + /* The config_base_address should hold the value of
> + *
Add dummy register support for the cp15, CRn=c15 registers.
config_base_register and power_control_register currently
default to 0, but may have improved support after the QOM
CPU patches are finished.
Signed-off-by: Mark Langsdorf
---
Changes from v5
Added handling for all c15 registers
