Hi Philippe,
On 10/3/18 1:26 AM, Philippe Mathieu-Daudé wrote:
> Hi Damien,
>
> On 10/2/18 4:24 PM, Damien Hedde wrote:
>> Add bus interface and uart reference clock inputs.
>>
>> Note: it is hard to find out from the doc what is the behavior when only one
>> of the clock is disabled.
>>
>> The
Hi Damien,
On 10/2/18 4:24 PM, Damien Hedde wrote:
> Add bus interface and uart reference clock inputs.
>
> Note: it is hard to find out from the doc what is the behavior when only one
> of the clock is disabled.
>
> The implemented behaviour is that register access needs both clock being
> act
Add bus interface and uart reference clock inputs.
Note: it is hard to find out from the doc what is the behavior when only one
of the clock is disabled.
The implemented behaviour is that register access needs both clock being active.
The bus interface control the mmios visibility
The reference
