Re: [Qemu-devel] [PATCH v5 10/28] target/mips: Add CPO PWSize register

2018-10-14 Thread Philippe Mathieu-Daudé
On Fri, Oct 12, 2018 at 6:49 PM Aleksandar Markovic wrote: > > From: Yongbok Kim > > Add PWSize register (CP0 Register 5, Select 7). > > The PWSize register configures hardware page table walking for TLB > refills. > > This register is required for the hardware page walker feature. It > exists on

[Qemu-devel] [PATCH v5 10/28] target/mips: Add CPO PWSize register

2018-10-12 Thread Aleksandar Markovic
From: Yongbok Kim Add PWSize register (CP0 Register 5, Select 7). The PWSize register configures hardware page table walking for TLB refills. This register is required for the hardware page walker feature. It exists only if Config3 PW bit is set to 1. It contains following fields: GDW (29..24