> From: Philippe Mathieu-Daudé
> > @@ -6948,6 +6969,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg,
> > int reg, int sel)
> > tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState,
> > CP0_SegCtl2));
> > rn = "SegCtl2";
> > break;
> > +case 5:
On Fri, Oct 12, 2018 at 6:47 PM Aleksandar Markovic
wrote:
>
> From: Yongbok Kim
>
> Add PWBase register (CP0 Register 5, Select 5).
>
> The PWBase register contains the Page Table Base virtual address.
>
> This register is required for the hardware page walker feature. It
> exists only if Config
> Subject: [PATCH v5 08/28] target/mips: Add CPO PWBase register
>
> From: Yongbok Kim
>
>Add PWBase register (CP0 Register 5, Select 5).
This and several other patches in this series contain letter "O" instead of
digit "0" in their title. This should be corrected.
Aleksandar
From: Yongbok Kim
Add PWBase register (CP0 Register 5, Select 5).
The PWBase register contains the Page Table Base virtual address.
This register is required for the hardware page walker feature. It
exists only if Config3 PW bit is set to 1.
Reviewed-by: Aleksandar Markovic
Signed-off-by: Yon
