On 6/3/2014 9:54 PM, Alexey Kardashevskiy wrote:
> On 06/04/2014 03:58 AM, Tom Musta wrote:
>> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>>> This adds TM (Transactional Memory) SPRs.
>>>
[ ... ]
>>
>> There are user-mode impacts here as well although I think we are a long
>> way off f
On 06/04/2014 03:58 AM, Tom Musta wrote:
> On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
>> This adds TM (Transactional Memory) SPRs.
>>
>> This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
>> handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
>> Since this
On 6/3/2014 4:27 AM, Alexey Kardashevskiy wrote:
> This adds TM (Transactional Memory) SPRs.
>
> This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
> handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
> Since this is not the only register like that and their n
This adds TM (Transactional Memory) SPRs.
This adds generic spr_read_prev_upper32()/spr_write_prev_upper32() to
handle upper half SPRs such as TEXASRU which is upper half of TEXASR.
Since this is not the only register like that and their numbers go
consequently, it makes sense to generalize the he
