On 1/19/19 10:51 PM, Richard Henderson wrote:
On 1/19/19 12:14 AM, Bastian Koppelmann wrote:
+static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
+{
+REQUIRE_FPU;
+if (a->rs1 == a->rs2) { /* FNEG */
+tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
+
On 1/19/19 12:14 AM, Bastian Koppelmann wrote:
> +static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsgnjn_s *a)
> +{
> +REQUIRE_FPU;
> +if (a->rs1 == a->rs2) { /* FNEG */
> +tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT32_MIN);
> +} else {
> +TCGv_i64 t0 = tcg_t
Reviewed-by: Richard Henderson
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
target/riscv/insn32.decode | 35 +++
target/riscv/insn_trans/trans_rvf.inc.c | 334
target/riscv/translate.c| 1 +
3 files changed, 370 inserti
