On 05/21/2015 02:47 AM, Yongbok Kim wrote:
> Fair enough. Actually I considered to pass the information but didn't
> bother as this way is so simple.
If you ever quit relying on a separate heck for atomics,
which you probably should, this would be incorrect.
r~
On 20/05/2015 18:09, Richard Henderson wrote:
> On 05/20/2015 08:12 AM, Yongbok Kim wrote:
>> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
>> index 73a8e45..58f02cf 100644
>> --- a/target-mips/op_helper.c
>> +++ b/target-mips/op_helper.c
>> @@ -2215,6 +2215,13 @@ void mips_cpu_do_
On 05/20/2015 08:12 AM, Yongbok Kim wrote:
> diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
> index 73a8e45..58f02cf 100644
> --- a/target-mips/op_helper.c
> +++ b/target-mips/op_helper.c
> @@ -2215,6 +2215,13 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr
> addr,
>
Release 6 requires misaligned memory access support for all ordinary memory
access instructions (for example, LW/SW, LWC1/SWC1).
However misaligned support is not provided for certain special memory accesses
such as atomics (for example, LL/SC).
Allows misaligned accesses from mips_cpu_do_unaligne
