On 15/12/2014 16:50, Dr. David Alan Gilbert wrote:
>> >
>> > if (val & UART_FCR_XFR) {
>> > +s->lsr |= UART_LSR_THRE;
>> > +s->thr_ipending = 1;
>> > fifo8_reset(&s->xmit_fifo);
>> > }
> Doesn't that break the assertion you added in patch 2
* Paolo Bonzini (pbonz...@redhat.com) wrote:
> When the transmit FIFO is emptied or enabled, the transmitter
> hold register is empty. When it is disabled, it is also emptied and
> in addition the previous contents of the transmitter hold register
> are discarded. In either case, the THRE bit in
When the transmit FIFO is emptied or enabled, the transmitter
hold register is empty. When it is disabled, it is also emptied and
in addition the previous contents of the transmitter hold register
are discarded. In either case, the THRE bit in LSR must be set and
THRI raised.
When the receive FI
