On 16 March 2016 at 06:32, Peter Maydell wrote:
> On 15 March 2016 at 21:40, Jean-Christophe DUBOIS
> wrote:
>> So do you mean I should define the 20 external lines (properties) and wire
>> all of them up with sysbus_connect_irq() in the i.MX6 SOC implementation
>> (fsl-imx6.c)?
>
> If you use q
On 15 March 2016 at 21:40, Jean-Christophe DUBOIS wrote:
> Well, each SPI controller has 4 possible CS lines to external devices and I
> have 5 SPI controllers.
>
> This makes 20 externally facing IRQ lines (these are output lines) to add to
> the i.MX6 soc object as properties (with a meaningful
Le 11/03/2016 00:57, Peter Maydell a écrit :
On 11 March 2016 at 02:24, Jean-Christophe DUBOIS wrote:
Le 10/03/2016 11:38, Peter Maydell a écrit :
On 2 March 2016 at 05:27, Jean-Christophe Dubois
wrote:
The sabrelite supports one SPI FLASH memory on SPI1
Signed-off-by: Jean-Christophe Duboi
On 11 March 2016 at 02:24, Jean-Christophe DUBOIS wrote:
> Le 10/03/2016 11:38, Peter Maydell a écrit :
>>
>> On 2 March 2016 at 05:27, Jean-Christophe Dubois
>> wrote:
>>>
>>> The sabrelite supports one SPI FLASH memory on SPI1
>>>
>>> Signed-off-by: Jean-Christophe Dubois
>>> ---
>>>
>>> +
>>>
Le 10/03/2016 11:38, Peter Maydell a écrit :
On 2 March 2016 at 05:27, Jean-Christophe Dubois wrote:
The sabrelite supports one SPI FLASH memory on SPI1
Signed-off-by: Jean-Christophe Dubois
---
+
+{
+/* Add the sst25vf016b NOR FLASH memory to first SPI */
+Object *spi_de
On 2 March 2016 at 05:27, Jean-Christophe Dubois wrote:
> The sabrelite supports one SPI FLASH memory on SPI1
>
> Signed-off-by: Jean-Christophe Dubois
> ---
>
> +
> +{
> +/* Add the sst25vf016b NOR FLASH memory to first SPI */
> +Object *spi_dev;
> +
> +spi_dev = obje
The sabrelite supports one SPI FLASH memory on SPI1
Signed-off-by: Jean-Christophe Dubois
---
Changes since v1:
* output a message and exit if RAM size is unsupported.
Changes since v2:
* Added include "qemu/osdep.h"
* Added access to controllers through properties.
hw/arm/Makefile.objs |
