Re: [Qemu-devel] [PATCH v3 11/12] i.MX: Add i.MX6 SOC implementation.

2016-03-10 Thread Peter Maydell
On 2 March 2016 at 05:27, Jean-Christophe Dubois wrote: > For now we only support the following devices: > * up to 4 Cortex A9 cores > * A9 MPCORE (SCU, GIC, TWD) > * 5 i.MX UARTs > * 2 EPIT timers > * 1 GPT timer > * 3 I2C controllers > * 7 GPIO controllers > * 6 SDHC controllers > * 5 SPI contro

[Qemu-devel] [PATCH v3 11/12] i.MX: Add i.MX6 SOC implementation.

2016-03-01 Thread Jean-Christophe Dubois
For now we only support the following devices: * up to 4 Cortex A9 cores * A9 MPCORE (SCU, GIC, TWD) * 5 i.MX UARTs * 2 EPIT timers * 1 GPT timer * 3 I2C controllers * 7 GPIO controllers * 6 SDHC controllers * 5 SPI controllers * 1 CCM device * 1 SRC device * various ROM/RAM areas. Signed-off-by: