On Fri, Feb 24, 2017 at 09:34:32AM +1100, Richard Henderson wrote:
> On 02/23/2017 05:40 PM, Nikunj A Dadhania wrote:
> > Richard Henderson writes:
> > > These functions are becoming quite large. Are they performance critical
> > > enough
> > > that they need to stay as inline code, or should th
On Thu, Feb 23, 2017 at 12:32:44PM +0530, Nikunj A Dadhania wrote:
> David Gibson writes:
>
> > -static void gen_read_xer(TCGv dst)
> >> +static void gen_read_xer(DisasContext *ctx, TCGv dst)
> >> {
> >> TCGv t0 = tcg_temp_new();
> >> TCGv t1 = tcg_temp_new();
> >> @@ -3715,15 +3719,30
On 02/23/2017 06:02 PM, Nikunj A Dadhania wrote:
David Gibson writes:
-static void gen_read_xer(TCGv dst)
+static void gen_read_xer(DisasContext *ctx, TCGv dst)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -3715,15 +3719,30 @@ static void gen_read_xer(TCGv dst)
tcg
On 02/23/2017 05:40 PM, Nikunj A Dadhania wrote:
Richard Henderson writes:
These functions are becoming quite large. Are they performance critical enough
that they need to stay as inline code, or should they be moved to helpers and
share code with cpu_read/write_xer?
Just to boot to login pr
David Gibson writes:
> -static void gen_read_xer(TCGv dst)
>> +static void gen_read_xer(DisasContext *ctx, TCGv dst)
>> {
>> TCGv t0 = tcg_temp_new();
>> TCGv t1 = tcg_temp_new();
>> @@ -3715,15 +3719,30 @@ static void gen_read_xer(TCGv dst)
>> tcg_gen_or_tl(t0, t0, t1);
>> t
Richard Henderson writes:
> Bah. Hit return too soon...
>
> On 02/22/2017 10:44 PM, Nikunj A Dadhania wrote:
>> -static void gen_read_xer(TCGv dst)
>> +static void gen_read_xer(DisasContext *ctx, TCGv dst)
>> {
>> TCGv t0 = tcg_temp_new();
>> TCGv t1 = tcg_temp_new();
>> @@ -3715,15 +
On Thu, Feb 23, 2017 at 10:39:47AM +0530, Nikunj A Dadhania wrote:
> David Gibson writes:
> >>
> >> diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
> >> index de3004b..89c1ccb 100644
> >> --- a/target/ppc/cpu.c
> >> +++ b/target/ppc/cpu.c
> >> @@ -23,8 +23,15 @@
> >>
> >> target_ulong cpu_rea
David Gibson writes:
>>
>> diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
>> index de3004b..89c1ccb 100644
>> --- a/target/ppc/cpu.c
>> +++ b/target/ppc/cpu.c
>> @@ -23,8 +23,15 @@
>>
>> target_ulong cpu_read_xer(CPUPPCState *env)
>> {
>> -return env->xer | (env->so << XER_SO) | (env->o
On Wed, Feb 22, 2017 at 05:14:36PM +0530, Nikunj A Dadhania wrote:
> POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
> and corresponding defines.
>
> Moreover, CA32 is updated when CA is updated and OV32 is updated when OV
> is updated.
>
> Arithmetic instructions:
> * A
On 02/22/2017 10:44 PM, Nikunj A Dadhania wrote:
POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
and corresponding defines.
Moreover, CA32 is updated when CA is updated and OV32 is updated when OV
is updated.
Arithmetic instructions:
* Addition and Substractions:
Bah. Hit return too soon...
On 02/22/2017 10:44 PM, Nikunj A Dadhania wrote:
-static void gen_read_xer(TCGv dst)
+static void gen_read_xer(DisasContext *ctx, TCGv dst)
{
TCGv t0 = tcg_temp_new();
TCGv t1 = tcg_temp_new();
@@ -3715,15 +3719,30 @@ static void gen_read_xer(TCGv dst)
POWER ISA 3.0 adds CA32 and OV32 status in 64-bit mode. Add the flags
and corresponding defines.
Moreover, CA32 is updated when CA is updated and OV32 is updated when OV
is updated.
Arithmetic instructions:
* Addition and Substractions:
addic, addic., subfic, addc, subfc, adde, subfe
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