On 03/02/2014 07:11 PM, Andreas Färber wrote:
> Hi Fabien,
>
> Am 14.02.2014 18:27, schrieb Fabien Chouteau:
>> On 02/14/2014 04:33 PM, Andreas Färber wrote:
>>> As for the other one you'll need to sort our who sends a pull if Blue
>>> doesn't resurface -
>>
>> I didn't see any message about this.
Hi Fabien,
Am 14.02.2014 18:27, schrieb Fabien Chouteau:
> On 02/14/2014 04:33 PM, Andreas Färber wrote:
>> As for the other one you'll need to sort our who sends a pull if Blue
>> doesn't resurface -
>
> I didn't see any message about this. Does anyone know why he's not around?
>
>> I note that
On 02/14/2014 04:33 PM, Andreas Färber wrote:
> As for the other one you'll need to sort our who sends a pull if Blue
> doesn't resurface -
I didn't see any message about this. Does anyone know why he's not around?
> I note that qemu-trivial is not CC'ed here and the
> patch probably isn't anyway
Am 14.02.2014 16:43, schrieb Sebastian Huber:
> On 2014-02-14 16:33, Andreas Färber wrote:
>>> @@ -5120,6 +5119,20 @@ static void disas_sparc_insn(DisasContext *
>>> dc, unsigned int insn)
>>> > case 0x37: /* stdc */
>>> > goto ncp_insn;
>>> > #endif
>>> >+#if
On 2014-02-14 16:33, Andreas Färber wrote:
@@ -5120,6 +5119,20 @@ static void disas_sparc_insn(DisasContext * dc, unsigned
int insn)
> case 0x37: /* stdc */
> goto ncp_insn;
> #endif
>+#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
>+
Am 14.02.2014 16:16, schrieb Sebastian Huber:
> The LEON3 processor has support for the CASA instruction which is
> normally only available for SPARC V9 processors. Binutils 2.24
> and GCC 4.9 will support this instruction for LEON3. GCC uses it to
> generate C11 atomic operations.
>
> The CAS s
The LEON3 processor has support for the CASA instruction which is
normally only available for SPARC V9 processors. Binutils 2.24
and GCC 4.9 will support this instruction for LEON3. GCC uses it to
generate C11 atomic operations.
The CAS synthetic instruction uses an ASI of 0x80. If TARGET_SPARC
