On Mon, Jul 29, 2013 at 04:46:22PM +0200, Vincenzo Maffione wrote:
> Actually it's not always zero because
>
> - presave() calls e1000_mit_timer(), which sets mit_timer_on to 0 and
> calls set_interrupt_cause(ICR);
>
> - if there are pending events, set_interrupt_cause(ICR) detects a
> raising ed
Actually it's not always zero because
- presave() calls e1000_mit_timer(), which sets mit_timer_on to 0 and
calls set_interrupt_cause(ICR);
- if there are pending events, set_interrupt_cause(ICR) detects a
raising edge, and doesn't filter out the interrupt since mit_timer_on
== 0. Therefore, the
On Fri, Jul 26, 2013 at 05:02:50PM +0200, Vincenzo Maffione wrote:
> +static const VMStateDescription vmstate_e1000_mit_state = {
> +.name = "e1000/mit_state",
> +.version_id = 1,
> +.minimum_version_id = 1,
> +.minimum_version_id_old = 1,
> +.fields= (VMStateField[]) {
> +
This patch partially implements the e1000 interrupt mitigation mechanisms.
Using a single QEMUTimer, it emulates the ITR register (which is the newer
mitigation register, recommended by Intel) and approximately emulates
RADV and TADV registers. TIDV and RDTR register functionalities are not
emulate
