Re: [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation

On 6/11/19 2:02 PM, Michael Rolnik wrote: > I am using this > one  > https://github.com/seharris/qemu-avr-tests/blob/master/free-rtos/Demo/AVR_ATMega2560_GCC/demo.elf > >   > it fails within __divmod

Re: [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation

I am using this one https://github.com/seharris/qemu-avr-tests/blob/master/free-rtos/Demo /AVR_ATMega2560_GCC/demo.elf it fails within __divmodsi4 function, there is rcall right after sbrc. Thanks for helping. On Tue, Jun 11, 2019 at 11:47 PM Richard Henderson < richard.hender...@linaro.org> wrot

Re: [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation

On 6/11/19 1:21 PM, Michael Rolnik wrote: > I merged all you fixes and I get an assert(use_icount) in cpu_loop_exec_tb > function, it happens on an instruction following SBRC. > what might cause it? No idea. What is your test case? And your tree, just in case there was an error in the merging.

Re: [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation

Hi Richard. I merged all you fixes and I get an assert(use_icount) in cpu_loop_exec_tb function, it happens on an instruction following SBRC. what might cause it? On Tue, Jun 11, 2019 at 12:20 AM Richard Henderson < richard.hender...@linaro.org> wrote: > On 6/6/19 12:30 PM, Michael Rolnik wrote:

Re: [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation

On 6/6/19 12:30 PM, Michael Rolnik wrote: > +if (ctx.check_skip > 0) { > +TCGLabel *skip = gen_new_label(); > +TCGLabel *done = gen_new_label(); > + > +tcg_gen_brcondi_tl(TCG_COND_NE, cpu_skip, 0, skip); > +translate(&ctx); > +

Re: [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation

On 6/6/19 12:30 PM, Michael Rolnik wrote: > +if ((ctx.cpc & (TARGET_PAGE_SIZE - 1)) == 0) { > +break; /* page boundary */ > +} This test isn't right, because this ended the TB if the *first* instruction was located on the page boundary. It also fails to allow for a 32-

Re: [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation

On 6/6/19 12:30 PM, Michael Rolnik wrote: > +enum { > +BS_NONE = 0, /* Nothing special (none of the below) */ > +BS_STOP = 1, /* We want to stop translation for any reason */ > +BS_BRANCH = 2, /* A branch condition is reached */ > +BS_EXCP = 3, /* An exception condition is reached *

Re: [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation

On 6/6/19 12:30 PM, Michael Rolnik wrote: > +target_long cpc; > +target_long npc; CPC gets copied back and forth to NPC, but is now otherwise unused. You can drop that. > +static void translate(DisasContext *ctx) > +{ > +uint32_t opcode; > +int res; > +/* PC points to words.

Re: [Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation

On 6/6/19 12:30 PM, Michael Rolnik wrote: > +void avr_cpu_tcg_init(void) > +{ > +int i; > + > +#define AVR_REG_OFFS(x) offsetof(CPUAVRState, x) > +cpu_pc = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(pc_w), "pc"); > +cpu_Cf = tcg_global_mem_new_i32(cpu_env, AVR_REG_OFFS(sregC), "Cf");

[Qemu-devel] [PATCH v21 4/7] target/avr: Add instruction translation

From: Sarah Harris This includes: - TCG translations for each instruction Signed-off-by: Michael Rolnik --- target/avr/translate.c | 2937 1 file changed, 2937 insertions(+) create mode 100644 target/avr/translate.c diff --git a/target/avr/translate.c