Alexander Graf wrote:
> Thomas Monjalon wrote:
> > I'm running Linux for SBC834x in Qemu. The interrupt controller and board
> > definition are not yet published.
>
> Wow, I didn't know there were still new products based on e300.
Sorry, I was not clear. By "not yet published", I mean that I've wr
Thomas Monjalon wrote:
> Alexander Graf wrote:
>
>> On 27.04.2010, at 17:31, Thomas Monjalon wrote:
>>
>>> Since commit 2ada0ed, "Return From Interrupt" is broken for PPC
>>> processors because the upper bits (POW, TGPR, ILE) of MSR were not
>>> cleared.
>>>
>> May I ask for your tes
Alexander Graf wrote:
> On 27.04.2010, at 17:31, Thomas Monjalon wrote:
> > Since commit 2ada0ed, "Return From Interrupt" is broken for PPC
> > processors because the upper bits (POW, TGPR, ILE) of MSR were not
> > cleared.
>
> May I ask for your test case or how you stumbled over this? I haven't s
On 27.04.2010, at 17:31, Thomas Monjalon wrote:
> From: Thomas Monjalon
>
> Since commit 2ada0ed, "Return From Interrupt" is broken for PPC processors
> because the upper bits (POW, TGPR, ILE) of MSR were not cleared.
May I ask for your test case or how you stumbled over this? I haven't seen a
From: Thomas Monjalon
Since commit 2ada0ed, "Return From Interrupt" is broken for PPC processors
because the upper bits (POW, TGPR, ILE) of MSR were not cleared.
Below is a representation of MSR bits:
0 .. 12 13 14 15 16 .. 23 24.. 31
— POW TGPR ILE EE PR
