Re: [Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts

2016-11-30 Thread Richard Henderson
On 11/29/2016 03:52 PM, Laurent Vivier wrote: > It doesn't work because we work with word/byte where the bit sign has > been extended to the long word. So in the case of 0 shift, with retrieve > C= and not 0. Ah, right. I wonder if it's better to always zero-extend the inputs for left-shifts, as

Re: [Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts

2016-11-29 Thread Laurent Vivier
Le 28/11/2016 à 15:54, Richard Henderson a écrit : > On 11/27/2016 11:35 AM, Laurent Vivier wrote: +tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64); >> This does not extract correctly the C flag when the opsize is word or byte. >> I think we should use a shift instead: >> >> -t

Re: [Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts

2016-11-28 Thread Richard Henderson
On 11/27/2016 11:35 AM, Laurent Vivier wrote: >> > +tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64); > This does not extract correctly the C flag when the opsize is word or byte. > I think we should use a shift instead: > > -tcg_gen_extr_i64_i32(QREG_CC_N, QREG_CC_C, t64); > - > -

Re: [Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts

2016-11-28 Thread Richard Henderson
On 11/27/2016 11:30 AM, Laurent Vivier wrote: > There is another bug on this one. > > Le 09/11/2016 à 14:46, Richard Henderson a écrit : >> diff --git a/target-m68k/translate.c b/target-m68k/translate.c >> index 4f224d7..1b3765f 100644 >> --- a/target-m68k/translate.c >> +++ b/target-m68k/translat

Re: [Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts

2016-11-28 Thread Richard Henderson
On 11/27/2016 09:53 AM, Laurent Vivier wrote: >> > +TCGv t0 = tcg_temp_new(); >> > +tcg_gen_sari_i32(QREG_CC_V, reg, bits - 1); >> > +tcg_gen_sari_i32(t0, t0, bits - count); > t0 is used unitialized, I think we should have here: > > t

Re: [Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts

2016-11-27 Thread Laurent Vivier
Le 09/11/2016 à 14:46, Richard Henderson a écrit : > diff --git a/target-m68k/translate.c b/target-m68k/translate.c > index 4f224d7..1b3765f 100644 > --- a/target-m68k/translate.c > +++ b/target-m68k/translate.c > +static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize) > +{ > +

Re: [Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts

2016-11-27 Thread Laurent Vivier
There is another bug on this one. Le 09/11/2016 à 14:46, Richard Henderson a écrit : > diff --git a/target-m68k/translate.c b/target-m68k/translate.c > index 4f224d7..1b3765f 100644 > --- a/target-m68k/translate.c > +++ b/target-m68k/translate.c > +static inline void shift_reg(DisasContext *s, uin

Re: [Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts

2016-11-27 Thread Laurent Vivier
Le 09/11/2016 à 14:46, Richard Henderson a écrit : > diff --git a/target-m68k/translate.c b/target-m68k/translate.c > index 4f224d7..1b3765f 100644 > --- a/target-m68k/translate.c > +++ b/target-m68k/translate.c > @@ -2883,48 +2883,205 @@ DISAS_INSN(addx_mem) > gen_store(s, opsize, addr_dest,

[Qemu-devel] [PATCH v2 3/5] target-m68k: Inline shifts

2016-11-09 Thread Richard Henderson
Also manage word and byte operands and fix the computation of overflow in the case of M68000 arithmetic shifts. Signed-off-by: Laurent Vivier Signed-off-by: Richard Henderson --- target-m68k/helper.c| 52 target-m68k/helper.h| 3 - target-m68k/translate.c | 214 +