On Wed, 31 Oct 2018 03:44:27 PDT (-0700), Bastian Koppelmann wrote:
On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
[...]
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+REQUIRE_FPU;
+
+TCGv t0 = tcg_temp_new();
+gen_hel
On 10/31/18 11:44 AM, Bastian Koppelmann wrote:
On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
[...]
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a,
uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+ REQUIRE_FPU;
+
+ TCGv t0 = tcg_temp_new();
+ gen_helper_fclass_d(t0,
On 10/20/18 9:14 AM, Bastian Koppelmann wrote:
[...]
+static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a, uint32_t insn)
+{
+#if defined(TARGET_RISCV64)
+REQUIRE_FPU;
+
+TCGv t0 = tcg_temp_new();
+gen_helper_fclass_d(t0, cpu_fpr[a->rs1]);
+gen_set_gpr(a->rd, t0);
+
On 10/20/18 8:14 AM, Bastian Koppelmann wrote:
> Signed-off-by: Bastian Koppelmann
> Signed-off-by: Peer Adelt
> ---
> v1 -> v2:
> - Add REQUIRE_FPU to arithm helpers
Reviewed-by: Richard Henderson
r~
Signed-off-by: Bastian Koppelmann
Signed-off-by: Peer Adelt
---
v1 -> v2:
- Add REQUIRE_FPU to arithm helpers
target/riscv/insn32.decode | 28 +++
target/riscv/insn_trans/trans_rvd.inc.c | 319
target/riscv/translate.c| 1 +
3 files c
