On Wed, Dec 30, 2015 at 6:35 PM, Peter Crosthwaite
wrote:
> On Wed, Dec 30, 2015 at 6:19 PM, Peter Crosthwaite
> wrote:
>> This concept might also be relevant to rPI work, where the SoC aliases
>> RAM. CC Andrew.
>>
>> On Wed, Dec 16, 2015 at 11:27 AM, Alistair Francis
>> wrote:
>>> The Xilinx Z
On Wed, Dec 30, 2015 at 6:19 PM, Peter Crosthwaite
wrote:
> This concept might also be relevant to rPI work, where the SoC aliases
> RAM. CC Andrew.
>
> On Wed, Dec 16, 2015 at 11:27 AM, Alistair Francis
> wrote:
>> The Xilinx ZynqMP SoC and EP108 board supports three memory regions:
>> - A 2GB
This concept might also be relevant to rPI work, where the SoC aliases
RAM. CC Andrew.
On Wed, Dec 16, 2015 at 11:27 AM, Alistair Francis
wrote:
> The Xilinx ZynqMP SoC and EP108 board supports three memory regions:
> - A 2GB region starting at 0
> - A 32GB region starting at 32GB
> - A 256GB
The Xilinx ZynqMP SoC and EP108 board supports three memory regions:
- A 2GB region starting at 0
- A 32GB region starting at 32GB
- A 256GB region starting at 768GB
This patch adds support for the first two memory regions, which is
automatically created based on the size specified by the QEMU
