Re: [Qemu-devel] [PATCH v2 08/12] target-arm: A64: add support for B and BL insns

2013-12-04 Thread Peter Maydell
On 4 December 2013 22:29, Richard Henderson wrote: > On 12/05/2013 11:14 AM, Peter Maydell wrote: >> It doesn't need initialization, does it? It's a static array, and we >> fill it as new temps are requested. So all we need to do is clear >> the count so it starts "empty". Or have I missed somethi

Re: [Qemu-devel] [PATCH v2 08/12] target-arm: A64: add support for B and BL insns

2013-12-04 Thread Richard Henderson
On 12/05/2013 11:14 AM, Peter Maydell wrote: > On 4 December 2013 21:55, Richard Henderson wrote: >> On 12/05/2013 08:33 AM, Peter Maydell wrote: >>> @@ -680,6 +720,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, >>> dc->condjmp = 0; >>> >>> dc->aarch64 = 1; >>> +dc->tmp_a6

Re: [Qemu-devel] [PATCH v2 08/12] target-arm: A64: add support for B and BL insns

2013-12-04 Thread Peter Maydell
On 4 December 2013 21:55, Richard Henderson wrote: > On 12/05/2013 08:33 AM, Peter Maydell wrote: >> @@ -680,6 +720,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, >> dc->condjmp = 0; >> >> dc->aarch64 = 1; >> +dc->tmp_a64_count = 0; >> dc->thumb = 0; >> dc->bswap

Re: [Qemu-devel] [PATCH v2 08/12] target-arm: A64: add support for B and BL insns

2013-12-04 Thread Richard Henderson
On 12/05/2013 08:33 AM, Peter Maydell wrote: > @@ -680,6 +720,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, > dc->condjmp = 0; > > dc->aarch64 = 1; > +dc->tmp_a64_count = 0; > dc->thumb = 0; > dc->bswap_code = 0; > dc->condexec_mask = 0; Still no initiali

[Qemu-devel] [PATCH v2 08/12] target-arm: A64: add support for B and BL insns

2013-12-04 Thread Peter Maydell
From: Alexander Graf Implement the B and BL instructions (PC relative branches and calls). For convenience in managing TCG temporaries which might be generated if a source register is the zero-register XZR, we provide a simple mechanism for creating a new temp which is automatically freed at the