Re: [Qemu-devel] [PATCH v2 05/21] RISC-V CPU Helpers

#ifdef CONFIG_USER_ONLY int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { return 0; } bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { return false; } int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int access_type, int mmu_idx) { cs->e

[Qemu-devel] [PATCH v2 05/21] RISC-V CPU Helpers

Privileged control and status register helpers and page fault handling. Signed-off-by: Michael Clark --- target/riscv/helper.c| 499 ++ target/riscv/helper.h| 78 ++ target/riscv/op_helper.c | 682 +++ 3 fil