On 2015-06-19 08:09, Pavel Dovgaluk wrote:
> > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > On 2015-06-18 12:02, Paolo Bonzini wrote:
> > >
> > > TCG can then use them to fill in an array stored inside the
> > > TranslationBlock, together with the host PC. Since the gen_opc_pc,
> > > gen
> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> On 2015-06-18 12:02, Paolo Bonzini wrote:
> >
> > TCG can then use them to fill in an array stored inside the
> > TranslationBlock, together with the host PC. Since the gen_opc_pc,
> > gen_opc_instr_start, gen_opc_icount arrays are inside tcg_
On 2015-06-18 12:02, Paolo Bonzini wrote:
>
>
> On 18/06/2015 11:42, Aurelien Jarno wrote:
> >> > QEMU could just always compute and store the restore_state information.
> >> > TCG needs to help filling it in (a new TCG opcode?), but it should be
> >> > easy.
> > Yes, that was another approach
On 18/06/2015 11:42, Aurelien Jarno wrote:
>> > QEMU could just always compute and store the restore_state information.
>> > TCG needs to help filling it in (a new TCG opcode?), but it should be
>> > easy.
> Yes, that was another approach I have in mind (I called it exception
> table in my othe
On 2015-06-18 11:29, Paolo Bonzini wrote:
> On 18/06/2015 11:08, Aurelien Jarno wrote:
> > For an i386 guest still on an x86 host, I get a 4% slower boot time by
> > not using retranslation (see patch below). This is not that much
> > compared to the complexity retranslation bring us.
>
> QEMU cou
On 18/06/2015 11:08, Aurelien Jarno wrote:
> For an i386 guest still on an x86 host, I get a 4% slower boot time by
> not using retranslation (see patch below). This is not that much
> compared to the complexity retranslation bring us.
QEMU could just always compute and store the restore_state inf
On 2015-06-18 10:16, Aurelien Jarno wrote:
> On x86, this patch brings a 5% boot time improvement on MIPS. One of the
> reason is that the TCG code generator has a good knowledge about which
> TCG ops or helpers can trigger an exception, so it can optimize out part
> of the instructions saving the
> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> On 2015-06-18 10:12, Pavel Dovgaluk wrote:
> > > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > > On 2015-06-17 15:41, Pavel Dovgalyuk wrote:
> > > > In icount mode every translation block looks as follows:
> > > >
> > > > if icount < n
On 2015-06-18 10:12, Pavel Dovgaluk wrote:
> > From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> > On 2015-06-17 15:41, Pavel Dovgalyuk wrote:
> > > In icount mode every translation block looks as follows:
> > >
> > > if icount < n then exit
> > > icount -= n
> > > instr1
> > > instr2
> > > ...
> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
> On 18 June 2015 at 08:12, Pavel Dovgaluk wrote:
> >> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> >> Looking at how icount work, I see it's basically a variable in the CPU
> >> state (icount_decr.u16.low), which is already accessed
On 18 June 2015 at 08:12, Pavel Dovgaluk wrote:
>> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
>> Looking at how icount work, I see it's basically a variable in the CPU
>> state (icount_decr.u16.low), which is already accessed from the TB.
>> Couldn't we adjust it using additional code befo
> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> On 2015-06-17 15:41, Pavel Dovgalyuk wrote:
> > In icount mode every translation block looks as follows:
> >
> > if icount < n then exit
> > icount -= n
> > instr1
> > instr2
> > ...
> > instrn
> > exit
> >
> > When one of these instructions in
> From: Aurelien Jarno [mailto:aurel...@aurel32.net]
> On 2015-06-17 15:41, Pavel Dovgalyuk wrote:
> > This set of patches fixes exception handling for MIPS and i386 targets.
> > These targets contain instructions that break correct execution in
> > icount/TCG modes (MIPS) and in regular TCG mode (
On 2015-06-17 15:41, Pavel Dovgalyuk wrote:
> In icount mode every translation block looks as follows:
>
> if icount < n then exit
> icount -= n
> instr1
> instr2
> ...
> instrn
> exit
>
> When one of these instructions initiates an exception, icount should be
> restored and adjusted number of i
On 2015-06-17 15:41, Pavel Dovgalyuk wrote:
> This set of patches fixes exception handling for MIPS and i386 targets.
> These targets contain instructions that break correct execution in
> icount/TCG modes (MIPS) and in regular TCG mode (i386).
Just to be clear, this is not something specific to
This set of patches fixes exception handling for MIPS and i386 targets.
These targets contain instructions that break correct execution in
icount/TCG modes (MIPS) and in regular TCG mode (i386).
Incorrect execution for i386 is causes by exceptions raised by MMU functions.
MMU helper functions are
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