Re: [Qemu-devel] [PATCH v2] target-arm: implement CPACR register logic for ARMv7

2014-05-23 Thread Peter Maydell
On 19 May 2014 21:56, Fabian Aggeler wrote: > In ARMv7 the CPACR register allows to control access rights to > coprocessor 0-13 interfaces. Bits corresponding to unimplemented > coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are > UNK/SBZP if VFP is not implemented and RAO/WI in some c

[Qemu-devel] [PATCH v2] target-arm: implement CPACR register logic for ARMv7

2014-05-19 Thread Fabian Aggeler
In ARMv7 the CPACR register allows to control access rights to coprocessor 0-13 interfaces. Bits corresponding to unimplemented coprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are UNK/SBZP if VFP is not implemented and RAO/WI in some cases. Treating TRCDIS as RAZ/WI since we neither impl