Re: [Qemu-devel] [PATCH v2] target/arm: Fix stlxp for aarch64_be

2018-01-08 Thread Peter Maydell
On 30 December 2017 at 22:56, Michael Weiser wrote: > ldxp loads two consecutive doublewords from memory regardless of CPU > endianness. On store, stlxp currently assumes to work with a 128bit > value and consequently switches order in big-endian mode. With this > change it packs the doublewords i

Re: [Qemu-devel] [PATCH v2] target/arm: Fix stlxp for aarch64_be

2018-01-02 Thread Michael Weiser
Hi Richard, On Mon, Jan 01, 2018 at 03:06:21PM -0800, Richard Henderson wrote: > > v2: > > - make it work for MTTCG as well by catering to the 128bit expectation > Reviewed-by: Richard Henderson > > + * 128bit store but two doulbewords stored consecutively */ >

Re: [Qemu-devel] [PATCH v2] target/arm: Fix stlxp for aarch64_be

2018-01-01 Thread Richard Henderson
On 12/30/2017 02:56 PM, Michael Weiser wrote: > ldxp loads two consecutive doublewords from memory regardless of CPU > endianness. On store, stlxp currently assumes to work with a 128bit > value and consequently switches order in big-endian mode. With this > change it packs the doublewords in rever

[Qemu-devel] [PATCH v2] target/arm: Fix stlxp for aarch64_be

2017-12-30 Thread Michael Weiser
ldxp loads two consecutive doublewords from memory regardless of CPU endianness. On store, stlxp currently assumes to work with a 128bit value and consequently switches order in big-endian mode. With this change it packs the doublewords in reverse order in anticipation of the 128bit big-endian stor