On Mon, Mar 05, 2018 at 06:53:48PM +0800, wei.guo.si...@gmail.com wrote:
> From: Simon Guo
>
> During migration, after MSR bits is synced, cpu_post_load() will use
> msr_mask to determine which PPC MSR bits will be applied into the target
> side. Hardware Transaction Memory(HTM) has been supporte
From: Simon Guo
During migration, after MSR bits is synced, cpu_post_load() will use
msr_mask to determine which PPC MSR bits will be applied into the target
side. Hardware Transaction Memory(HTM) has been supported since Power8,
but TS0/TS1 bit was not in msr_mask yet. That will prevent target K
