Re: [Qemu-devel] [PATCH v1 17/21] SiFive RISC-V UART Device

2018-01-04 Thread Michael Clark
On Thu, Jan 4, 2018 at 3:57 AM, KONRAD Frederic wrote: > Hi all, > > > On 01/03/2018 01:44 AM, Michael Clark wrote: > >> QEMU model of the UART on the SiFive E300 and U500 series SOCs. >> BBL supports the SiFive UART for early console access via the SBI >> (Supervisor Binary Interface) and the li

Re: [Qemu-devel] [PATCH v1 17/21] SiFive RISC-V UART Device

2018-01-04 Thread Michael Clark
On Fri, 5 Jan 2018 at 9:53 AM, Antony Pavlov wrote: > On Wed, 3 Jan 2018 13:44:21 +1300 > Michael Clark wrote: > > > QEMU model of the UART on the SiFive E300 and U500 series SOCs. > > BBL supports the SiFive UART for early console access via the SBI > > (Supervisor Binary Interface) and the li

Re: [Qemu-devel] [PATCH v1 17/21] SiFive RISC-V UART Device

2018-01-04 Thread Antony Pavlov
On Wed, 3 Jan 2018 13:44:21 +1300 Michael Clark wrote: > QEMU model of the UART on the SiFive E300 and U500 series SOCs. > BBL supports the SiFive UART for early console access via the SBI > (Supervisor Binary Interface) and the linux kernel SBI console. > > The SiFive UART implements the pre q

Re: [Qemu-devel] [PATCH v1 17/21] SiFive RISC-V UART Device

2018-01-03 Thread KONRAD Frederic
Hi all, On 01/03/2018 01:44 AM, Michael Clark wrote: QEMU model of the UART on the SiFive E300 and U500 series SOCs. BBL supports the SiFive UART for early console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The SiFive UART implements the pre qom legacy in

[Qemu-devel] [PATCH v1 17/21] SiFive RISC-V UART Device

2018-01-02 Thread Michael Clark
QEMU model of the UART on the SiFive E300 and U500 series SOCs. BBL supports the SiFive UART for early console access via the SBI (Supervisor Binary Interface) and the linux kernel SBI console. The SiFive UART implements the pre qom legacy interface consistent with the 16550a UART in 'hw/char/seri