Re: [Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState

On Fri, 23 Aug 2019 16:38:02 PDT (-0700), Alistair Francis wrote: As the MIP CSR is 32-bits to allow atomic_read on 32-bit hosts the vsip is 32-bit as well. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 17 + 1 file changed, 17 insertions(+) diff --git a/target/risc

[Qemu-devel] [PATCH v1 05/28] target/riscv: Add the Hypervisor CSRs to CPUState

As the MIP CSR is 32-bits to allow atomic_read on 32-bit hosts the vsip is 32-bit as well. Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 17 + 1 file changed, 17 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3a95c41428..4c342e7a79 100644 ---