Re: [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode

2019-09-10 Thread Palmer Dabbelt
On Fri, 23 Aug 2019 16:37:57 PDT (-0700), Alistair Francis wrote: Signed-off-by: Alistair Francis There's really no description of what this does, either in the commit message or as a comment. --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_bits.h | 6 ++ target/riscv/cpu_hel

Re: [Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode

2019-08-27 Thread Chih-Min Chao
On Sat, Aug 24, 2019 at 7:50 AM Alistair Francis wrote: > Signed-off-by: Alistair Francis > --- > target/riscv/cpu.h| 2 ++ > target/riscv/cpu_bits.h | 6 ++ > target/riscv/cpu_helper.c | 23 +++ > 3 files changed, 31 insertions(+) > > diff --git a/target/ris

[Qemu-devel] [PATCH v1 03/28] target/riscv: Add the force HS exception mode

2019-08-23 Thread Alistair Francis
Signed-off-by: Alistair Francis --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_bits.h | 6 ++ target/riscv/cpu_helper.c | 23 +++ 3 files changed, 31 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0ef1ecb0e0..3a95c41428 100644 --- a/t