On Wed, May 6, 2015 at 6:16 AM, Peter Maydell wrote:
> On 6 May 2015 at 14:08, Peter Crosthwaite
> wrote:
>> Ergh, I have to backpeddle again (sry for the noise), patches still
>> doesnt work for me (serves me right for not looking at the year of
>> submission dates). Latest patches I have from
On Wed, May 6, 2015 at 6:26 AM, Peter Maydell wrote:
> On 6 May 2015 at 14:21, Peter Crosthwaite
> wrote:
>> On Wed, May 6, 2015 at 6:18 AM, Peter Maydell
>> wrote:
>>> On 6 May 2015 at 14:02, Peter Crosthwaite
>>> wrote:
Actually NVM. I got it working on a diff machine. Did you have an
On 6 May 2015 at 14:21, Peter Crosthwaite wrote:
> On Wed, May 6, 2015 at 6:18 AM, Peter Maydell
> wrote:
>> On 6 May 2015 at 14:02, Peter Crosthwaite
>> wrote:
>>> Actually NVM. I got it working on a diff machine. Did you have any
>>> thoughts on the GICC mirror issue while I respin?
>>
>> Yo
On Wed, May 6, 2015 at 6:18 AM, Peter Maydell wrote:
> On 6 May 2015 at 14:02, Peter Crosthwaite
> wrote:
>> Actually NVM. I got it working on a diff machine. Did you have any
>> thoughts on the GICC mirror issue while I respin?
>
> You mean the thing where the GICC might not be at the bottom of
On 6 May 2015 at 14:02, Peter Crosthwaite wrote:
> Actually NVM. I got it working on a diff machine. Did you have any
> thoughts on the GICC mirror issue while I respin?
You mean the thing where the GICC might not be at the bottom of
a 64K page? Just map it wherever it lives in the hardware you'r
On 6 May 2015 at 14:08, Peter Crosthwaite wrote:
> Ergh, I have to backpeddle again (sry for the noise), patches still
> doesnt work for me (serves me right for not looking at the year of
> submission dates). Latest patches I have from
>
> http://wiki.qemu.org/patches/patches.json
>
> is:
>
> Mess
On Wed, May 6, 2015 at 6:02 AM, Peter Crosthwaite
wrote:
> On Wed, May 6, 2015 at 5:14 AM, Peter Maydell
> wrote:
>> On 1 May 2015 at 18:25, Peter Crosthwaite
>> wrote:
>>> Ping!
>>>
>>> On Fri, Apr 24, 2015 at 1:28 PM, Peter Crosthwaite
>>> wrote:
Hi Peter and all,
Xilinx's ne
On Wed, May 6, 2015 at 5:14 AM, Peter Maydell wrote:
> On 1 May 2015 at 18:25, Peter Crosthwaite
> wrote:
>> Ping!
>>
>> On Fri, Apr 24, 2015 at 1:28 PM, Peter Crosthwaite
>> wrote:
>>> Hi Peter and all,
>>>
>>> Xilinx's next gen SoC has been announced. This series adds a SoC and
>>> board.
>
>
On Wed, May 6, 2015 at 5:14 AM, Peter Maydell wrote:
> On 1 May 2015 at 18:25, Peter Crosthwaite
> wrote:
>> Ping!
>>
>> On Fri, Apr 24, 2015 at 1:28 PM, Peter Crosthwaite
>> wrote:
>>> Hi Peter and all,
>>>
>>> Xilinx's next gen SoC has been announced. This series adds a SoC and
>>> board.
>
>
On 1 May 2015 at 18:25, Peter Crosthwaite wrote:
> Ping!
>
> On Fri, Apr 24, 2015 at 1:28 PM, Peter Crosthwaite
> wrote:
>> Hi Peter and all,
>>
>> Xilinx's next gen SoC has been announced. This series adds a SoC and
>> board.
Neither patchwork nor patches seem to have the complete set of
these
Ping!
On Fri, Apr 24, 2015 at 1:28 PM, Peter Crosthwaite
wrote:
> Hi Peter and all,
>
> Xilinx's next gen SoC has been announced. This series adds a SoC and
> board.
>
> Series start with addition of ARM cortex A53 support (P1 and P2). The
> Soc skeleton is then added with GIC, EMACs and UARTs ar
Hi Peter and all,
Xilinx's next gen SoC has been announced. This series adds a SoC and
board.
Series start with addition of ARM cortex A53 support (P1 and P2). The
Soc skeleton is then added with GIC, EMACs and UARTs are added. The
pre-existing models for GEM and UART are not SoC friendly (no vis
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