01.06.2015 05:51, Peter Crosthwaite wrote:
> On Thu, May 28, 2015 at 11:22 PM, Sai Pavan Boddu
> wrote:
>> This patch corrects the Rx buffer size field mask to mask bits 23 to 16
>>
>> Signed-off-by: Sai Pavan Boddu
>> Reviewed-by: Alistair Francis
>
> Matches Xilinx UG585 documentation.
>
> R
On Thu, May 28, 2015 at 11:22 PM, Sai Pavan Boddu
wrote:
> This patch corrects the Rx buffer size field mask to mask bits 23 to 16
>
> Signed-off-by: Sai Pavan Boddu
> Reviewed-by: Alistair Francis
Matches Xilinx UG585 documentation.
Reviewed-by: Peter Crosthwaite
Can this go via the trivial
This patch corrects the Rx buffer size field mask to mask bits 23 to 16
Signed-off-by: Sai Pavan Boddu
Reviewed-by: Alistair Francis
---
hw/net/cadence_gem.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
index dafe914..494a
