[Qemu-devel] [PATCH 8/9] sparc64: interrupt trap handling

2010-01-07 Thread Igor V. Kovalenko
From: Igor V. Kovalenko cpu_check_irqs - handle SOFTINT register TICK and STICK timer bits - only check interrupt levels greater than PIL value - handle preemption by higher level traps cpu_exec - handle CPU_INTERRUPT_HARD only if interrupts are enabled - PIL 15 is not special level on sparcv9

Re: [Qemu-devel] [PATCH 8/9] sparc64: interrupt trap handling

2010-01-07 Thread Igor Kovalenko
On Wed, Jan 6, 2010 at 8:00 PM, Blue Swirl wrote: > On Tue, Jan 5, 2010 at 11:19 PM, Igor V. Kovalenko > wrote: >> From: Igor V. Kovalenko >> >> cpu_check_irqs >> - handle SOFTINT register TICK and STICK timer bits >> - only check interrupt levels greater than PIL value >> - handle preemption by

Re: [Qemu-devel] [PATCH 8/9] sparc64: interrupt trap handling

2010-01-06 Thread Blue Swirl
On Tue, Jan 5, 2010 at 11:19 PM, Igor V. Kovalenko wrote: > From: Igor V. Kovalenko > > cpu_check_irqs > - handle SOFTINT register TICK and STICK timer bits > - only check interrupt levels greater than PIL value > - handle preemption by higher level traps > > cpu_exec > - handle CPU_INTERRUPT_HAR

[Qemu-devel] [PATCH 8/9] sparc64: interrupt trap handling

2010-01-05 Thread Igor V. Kovalenko
From: Igor V. Kovalenko cpu_check_irqs - handle SOFTINT register TICK and STICK timer bits - only check interrupt levels greater than PIL value - handle preemption by higher level traps cpu_exec - handle CPU_INTERRUPT_HARD only if interrupts are enabled - PIL 15 is not special level on sparcv9