Re: [Qemu-devel] [PATCH 5/8] target-arm: A64: Add logic ops from SIMD 3 same group

2014-01-21 Thread Richard Henderson
On 01/17/2014 10:44 AM, Peter Maydell wrote: > +/* AND, BIC, ORR, ORN */ > +if (extract32(size, 0, 1)) { > +tcg_gen_not_i64(tcg_op2, tcg_op2); > +} > +if (extract32(size, 1, 1)) { > +tcg_gen_or_i64(tcg_res[pass], tcg_op

[Qemu-devel] [PATCH 5/8] target-arm: A64: Add logic ops from SIMD 3 same group

2014-01-17 Thread Peter Maydell
From: Alex Bennée Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL, BIT and BIF) from the SIMD 3 register same group (C3.6.16). Signed-off-by: Alex Bennée Signed-off-by: Peter Maydell --- target-arm/translate-a64.c | 68 +- 1 fil