On 08/22/2017 10:57 PM, Stafford Horne wrote:
> Wire in ompic and add basic support for SMP. The OpenRISC is special in
> that interrupts for devices are routed to each core's PIC. This is
> achieved using the qemu_irq_split utility, but this currently limits
> OpenRISC to 2 cores.
>
> This mode
Wire in ompic and add basic support for SMP. The OpenRISC is special in
that interrupts for devices are routed to each core's PIC. This is
achieved using the qemu_irq_split utility, but this currently limits
OpenRISC to 2 cores.
This models the reference architecture described in the OpenRISC sp
