Re: [Qemu-devel] [PATCH 4/5] hw/mips/malta: Only accept 'monitor' pflash of 4MiB

2019-03-06 Thread Markus Armbruster
Philippe Mathieu-Daudé writes: > The Malta 'mother' board can use various 'daughter' core cards [1]. > QEMU only models the CoreLV card. > > The CoreLV card provides [2] a Galileo GT64120 as North bridge, > connecting the CPU via the 'CBUS'. The CBUS also connects a 'Monitor > flash' memory and m

Re: [Qemu-devel] [PATCH 4/5] hw/mips/malta: Only accept 'monitor' pflash of 4MiB

2019-03-06 Thread Philippe Mathieu-Daudé
On 3/6/19 12:53 AM, Richard Henderson wrote: > On 3/5/19 8:28 AM, Philippe Mathieu-Daudé wrote: >> + >> +if (blk_getlength(pflash_blk) != FLASH_SIZE) { >> +error_report("Malta CoreLV card expects a bios of 4MB"); >> +exit(1); >> +} > > Indentation is

Re: [Qemu-devel] [PATCH 4/5] hw/mips/malta: Only accept 'monitor' pflash of 4MiB

2019-03-05 Thread Richard Henderson
On 3/5/19 8:28 AM, Philippe Mathieu-Daudé wrote: > + > +if (blk_getlength(pflash_blk) != FLASH_SIZE) { > +error_report("Malta CoreLV card expects a bios of 4MB"); > +exit(1); > +} Indentation is off, somehow. Tabs or extra spaces? r~

[Qemu-devel] [PATCH 4/5] hw/mips/malta: Only accept 'monitor' pflash of 4MiB

2019-03-05 Thread Philippe Mathieu-Daudé
The Malta 'mother' board can use various 'daughter' core cards [1]. QEMU only models the CoreLV card. The CoreLV card provides [2] a Galileo GT64120 as North bridge, connecting the CPU via the 'CBUS'. The CBUS also connects a 'Monitor flash' memory and maps it to the CPU RESET vector. The Monitor