Re: [Qemu-devel] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions

2016-10-25 Thread Nikunj A Dadhania
Richard Henderson writes: > On 10/24/2016 11:02 PM, Nikunj A Dadhania wrote: >> Richard Henderson writes: >> >> >>> We already have rol32 and rol64. >>> >>> Which I see are broken for shift == 0. >> >> I tried with different shift (including 0) in a test program, and the >> result is as expec

Re: [Qemu-devel] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions

2016-10-25 Thread Richard Henderson
On 10/24/2016 11:02 PM, Nikunj A Dadhania wrote: > Richard Henderson writes: > > >> We already have rol32 and rol64. >> >> Which I see are broken for shift == 0. > > I tried with different shift (including 0) in a test program, and the > result is as expected: > > 0: ccddeeff > > static inlin

Re: [Qemu-devel] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions

2016-10-24 Thread Nikunj A Dadhania
Richard Henderson writes: > We already have rol32 and rol64. > > Which I see are broken for shift == 0. I tried with different shift (including 0) in a test program, and the result is as expected: 0: ccddeeff static inline unsigned int rol32(unsigned int word, unsigned int shift) { return (

Re: [Qemu-devel] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions

2016-10-24 Thread Nikunj A Dadhania
Richard Henderson writes: > On 10/24/2016 09:08 PM, Nikunj A Dadhania wrote: >> Richard Henderson writes: >> >>> On 10/24/2016 02:14 AM, Nikunj A Dadhania wrote: +#define EXTRACT_BITS(size) \ +static inline uint##size##_t extract_bits_u##siz

Re: [Qemu-devel] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions

2016-10-24 Thread Richard Henderson
On 10/24/2016 09:08 PM, Nikunj A Dadhania wrote: Richard Henderson writes: On 10/24/2016 02:14 AM, Nikunj A Dadhania wrote: +#define EXTRACT_BITS(size) \ +static inline uint##size##_t extract_bits_u##size(uint##size##_t reg, \ +

Re: [Qemu-devel] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions

2016-10-24 Thread Nikunj A Dadhania
Richard Henderson writes: > On 10/24/2016 02:14 AM, Nikunj A Dadhania wrote: >> +#define EXTRACT_BITS(size) \ >> +static inline uint##size##_t extract_bits_u##size(uint##size##_t reg, \ >> + uint##size

Re: [Qemu-devel] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions

2016-10-24 Thread Richard Henderson
On 10/24/2016 02:14 AM, Nikunj A Dadhania wrote: > +#define EXTRACT_BITS(size) \ > +static inline uint##size##_t extract_bits_u##size(uint##size##_t reg, \ > + uint##size##_t start, \ > +

[Qemu-devel] [PATCH 3/4] target-ppc: add vrldnmi and vrlwmi instructions

2016-10-24 Thread Nikunj A Dadhania
From: "Gautham R. Shenoy" vrldmi: Vector Rotate Left Dword then Mask Insert vrlwmi: Vector Rotate Left Word then Mask Insert Signed-off-by: Gautham R. Shenoy Signed-off-by: Bharata B Rao Signed-off-by: Nikunj A Dadhania --- disas/ppc.c | 2 + target-ppc/helper.h