On 7/16/19 11:08 PM, tony.ngu...@bt.com wrote:
> diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
> index baa61719ad..11debb7dda 100644
> --- a/accel/tcg/cputlb.c
> +++ b/accel/tcg/cputlb.c
> @@ -731,7 +731,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong
> vaddr,
>
Notice new attribute, byte swap, and force the transaction through the
memory slow path.
Required by architectures that can invert endianness of memory
transaction, e.g. SPARC64 has the Invert Endian TTE bit.
Signed-off-by: Tony Nguyen
---
accel/tcg/cputlb.c | 10 +-
include/exec/m
