> -Original Message-
> From: Wood Scott-B07421
> Sent: Wednesday, October 10, 2012 4:08 AM
> To: Bhushan Bharat-R65777
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; ag...@suse.de;
> afaer...@suse.de;
> Bhushan Bharat-R65777
> Subject: Re: [Qemu-devel] [PATCH
On 10/09/2012 01:19:10 PM, Bharat Bhushan wrote:
+static int e500_ccsr_initfn(SysBusDevice *dev)
+{
+PPCE500CCSRState *pci_ccsr;
+
+pci_ccsr = CCSR(dev);
+memory_region_init(&pci_ccsr->ccsr_space, "e500-ccsr",
+ MPC8544_CCSRBAR_SIZE);
+return 0;
+}
Is this
Am 09.10.2012 20:19, schrieb Bharat Bhushan:
> PCI Root complex have TYPE-1 configuration header while PCI endpoint
> have type-0 configuration header. The type-1 configuration header have
> a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
> address space to CCSR address space
PCI Root complex have TYPE-1 configuration header while PCI endpoint
have type-0 configuration header. The type-1 configuration header have
a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
address space to CCSR address space. This can used for 2 purposes: 1)
for MSI interrupt
