On Tue, Apr 18, 2017 at 04:15:51PM +1000, Tim 'mithro' Ansell wrote:
> Exception Prefix High (EPH) control bit of the Supervision Register
> (SR).
>
> The significant bits (31-12) of the vector offset address for each
> exception depend on the setting of the Supervision Register (SR)'s EPH
> bit a
Exception Prefix High (EPH) control bit of the Supervision Register
(SR).
The significant bits (31-12) of the vector offset address for each
exception depend on the setting of the Supervision Register (SR)'s EPH
bit and the Exception Vector Base Address Register (EVBAR).
If SR[EPH] is set, the ve
