Re: [Qemu-devel] [PATCH 2/2] s390x/css: fix bits must be zero check for TIC

2017-07-27 Thread Cornelia Huck
On Thu, 27 Jul 2017 15:40:33 +0200 Halil Pasic wrote: > [Re-posting my previous reply because I've accidentally > dropped almost all addressees.] > > On 07/27/2017 10:01 AM, Cornelia Huck wrote: > > On Wed, 26 Jul 2017 00:44:42 +0200 > > Halil Pasic wrote: > > > >> According to the PoP bit p

Re: [Qemu-devel] [PATCH 2/2] s390x/css: fix bits must be zero check for TIC

2017-07-27 Thread Halil Pasic
[Re-posting my previous reply because I've accidentally dropped almost all addressees.] On 07/27/2017 10:01 AM, Cornelia Huck wrote: > On Wed, 26 Jul 2017 00:44:42 +0200 > Halil Pasic wrote: > >> According to the PoP bit positions 0-3 and 8-32 of the format-1 CCW must >> contain zeros. Bits 0-3

Re: [Qemu-devel] [PATCH 2/2] s390x/css: fix bits must be zero check for TIC

2017-07-27 Thread Halil Pasic
On 07/27/2017 10:01 AM, Cornelia Huck wrote: > On Wed, 26 Jul 2017 00:44:42 +0200 > Halil Pasic wrote: > >> According to the PoP bit positions 0-3 and 8-32 of the format-1 CCW must >> contain zeros. Bits 0-3 are already covered by cmd_code validity >> checking, and bit 32 is covered by the CCW

Re: [Qemu-devel] [PATCH 2/2] s390x/css: fix bits must be zero check for TIC

2017-07-27 Thread Dong Jia Shi
* Cornelia Huck [2017-07-27 10:32:14 +0200]: > On Wed, 26 Jul 2017 00:44:42 +0200 > Halil Pasic wrote: > > > According to the PoP bit positions 0-3 and 8-32 of the format-1 CCW must > > contain zeros. Bits 0-3 are already covered by cmd_code validity > > checking, and bit 32 is covered by the

Re: [Qemu-devel] [PATCH 2/2] s390x/css: fix bits must be zero check for TIC

2017-07-27 Thread Cornelia Huck
On Wed, 26 Jul 2017 00:44:42 +0200 Halil Pasic wrote: > According to the PoP bit positions 0-3 and 8-32 of the format-1 CCW must > contain zeros. Bits 0-3 are already covered by cmd_code validity > checking, and bit 32 is covered by the CCW address checking. > > Bits 8-31 correspond to CCW1.fla

Re: [Qemu-devel] [PATCH 2/2] s390x/css: fix bits must be zero check for TIC

2017-07-27 Thread Cornelia Huck
On Wed, 26 Jul 2017 00:44:42 +0200 Halil Pasic wrote: > According to the PoP bit positions 0-3 and 8-32 of the format-1 CCW must > contain zeros. Bits 0-3 are already covered by cmd_code validity > checking, and bit 32 is covered by the CCW address checking. > > Bits 8-31 correspond to CCW1.fla

Re: [Qemu-devel] [PATCH 2/2] s390x/css: fix bits must be zero check for TIC

2017-07-26 Thread Dong Jia Shi
* Halil Pasic [2017-07-26 13:38:33 +0200]: > > > On 07/26/2017 05:01 AM, Dong Jia Shi wrote: > > Hello Halil, > > > > * Halil Pasic [2017-07-26 00:44:42 +0200]: > > > >> According to the PoP bit positions 0-3 and 8-32 of the format-1 CCW must > >> contain zeros. Bits 0-3 are already covered

Re: [Qemu-devel] [PATCH 2/2] s390x/css: fix bits must be zero check for TIC

2017-07-26 Thread Halil Pasic
On 07/26/2017 05:01 AM, Dong Jia Shi wrote: > Hello Halil, > > * Halil Pasic [2017-07-26 00:44:42 +0200]: > >> According to the PoP bit positions 0-3 and 8-32 of the format-1 CCW must >> contain zeros. Bits 0-3 are already covered by cmd_code validity >> checking, and bit 32 is covered by the

Re: [Qemu-devel] [PATCH 2/2] s390x/css: fix bits must be zero check for TIC

2017-07-25 Thread Dong Jia Shi
Hello Halil, * Halil Pasic [2017-07-26 00:44:42 +0200]: > According to the PoP bit positions 0-3 and 8-32 of the format-1 CCW must > contain zeros. Bits 0-3 are already covered by cmd_code validity > checking, and bit 32 is covered by the CCW address checking. > > Bits 8-31 correspond to CCW1.

[Qemu-devel] [PATCH 2/2] s390x/css: fix bits must be zero check for TIC

2017-07-25 Thread Halil Pasic
According to the PoP bit positions 0-3 and 8-32 of the format-1 CCW must contain zeros. Bits 0-3 are already covered by cmd_code validity checking, and bit 32 is covered by the CCW address checking. Bits 8-31 correspond to CCW1.flags and CCW1.count. Currently we only check for the absence of cer