Re: [Qemu-devel] [PATCH 11/14] ppc: store CR registers in 32 1-bit registers

2014-09-19 Thread Paolo Bonzini
Il 18/09/2014 22:25, Tom Musta ha scritto: > This breaks what you did in patch 5, which used LE bit numbering to > perform shifts. Yeah, I change "1 << x" to "8 >> x" in this patch for the fcmp helpers, but not the others. > And it breaks other code that uses the old LE > convention. I'll fix it

Re: [Qemu-devel] [PATCH 11/14] ppc: store CR registers in 32 1-bit registers

2014-09-18 Thread Tom Musta
On 9/15/2014 10:03 AM, Paolo Bonzini wrote: > This makes comparisons much smaller and faster. The speedup is > approximately 10% on user-mode emulation on x86 host, 3-4% on PPC. > > Note that CRF_* constants are flipped to match PowerPC's big > bit-endianness. Previously, the CR register was eff

[Qemu-devel] [PATCH 11/14] ppc: store CR registers in 32 1-bit registers

2014-09-15 Thread Paolo Bonzini
This makes comparisons much smaller and faster. The speedup is approximately 10% on user-mode emulation on x86 host, 3-4% on PPC. Note that CRF_* constants are flipped to match PowerPC's big bit-endianness. Previously, the CR register was effectively stored in mixed endianness, so now there is l