emu-devel] [PATCH 1/7] target-mips: fix DSP loads with rd = 0
>
> When rd is 0, which still need to do the actually load to possibly
> generate a TLB exception.
>
> Signed-off-by: Aurelien Jarno
> ---
> target-mips/translate.c |5 -
> 1 file changed, 5 deletions(-
When rd is 0, which still need to do the actually load to possibly
generate a TLB exception.
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c |5 -
1 file changed, 5 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 01b48fa..c3e00c5 100644
--- a/
