On Thu, 2014-07-24 at 07:24 +0800, Le Tan wrote:
> Hi Stefan,
>
> 2014-07-24 4:29 GMT+08:00 Stefan Weil :
> > Am 22.07.2014 17:47, schrieb Le Tan:
> >> Add support for emulating Intel IOMMU according to the VT-d specification
> >> for
> >> the q35 chipset machine. Implement the logic for DMAR (DM
Hi Stefan,
2014-07-24 4:29 GMT+08:00 Stefan Weil :
> Am 22.07.2014 17:47, schrieb Le Tan:
>> Add support for emulating Intel IOMMU according to the VT-d specification for
>> the q35 chipset machine. Implement the logic for DMAR (DMA remapping) without
>> PASID support. Use register-based invalidat
Hi Paolo,
2014-07-23 15:58 GMT+08:00 Paolo Bonzini :
> Il 22/07/2014 17:47, Le Tan ha scritto:
>> +static inline void define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t
>> val,
>> +uint64_t wmask, uint64_t w1cmask)
>> +{
>> +*((uint64_t *)&s->csr[addr]) = val;
>
> A
Am 22.07.2014 17:47, schrieb Le Tan:
> Add support for emulating Intel IOMMU according to the VT-d specification for
> the q35 chipset machine. Implement the logic for DMAR (DMA remapping) without
> PASID support. Use register-based invalidation for context-cache invalidation
> and IOTLB invalidati
Il 22/07/2014 17:47, Le Tan ha scritto:
> +static inline void define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val,
> +uint64_t wmask, uint64_t w1cmask)
> +{
> +*((uint64_t *)&s->csr[addr]) = val;
All these casts are not endian-safe. Please use ldl_le_p, ldq_le_p,
Hi Michael,
Thanks very much for your careful reviewing!
2014-07-23 4:05 GMT+08:00 Michael S. Tsirkin :
> On Tue, Jul 22, 2014 at 11:47:48PM +0800, Le Tan wrote:
>> Add support for emulating Intel IOMMU according to the VT-d specification for
>> the q35 chipset machine. Implement the logic for DMA
On Tue, Jul 22, 2014 at 11:47:48PM +0800, Le Tan wrote:
> Add support for emulating Intel IOMMU according to the VT-d specification for
> the q35 chipset machine. Implement the logic for DMAR (DMA remapping) without
> PASID support. Use register-based invalidation for context-cache invalidation
> a
Add support for emulating Intel IOMMU according to the VT-d specification for
the q35 chipset machine. Implement the logic for DMAR (DMA remapping) without
PASID support. Use register-based invalidation for context-cache invalidation
and IOTLB invalidation.
Basic fault reporting and caching are not
