Hi Peter,
thanks for the review! I'll rework the patch ASAP.
> Is it better to just model the GPIO controller as a standalone GPIO,
> and leave the mio vs emio distinction to the SoC/Board level?
>
> This would mean the bank GPIOs are on the top level entity, and the
> core would then have no EM
On Tue, Dec 30, 2014 at 5:13 AM, Colin Leitner
wrote:
> Based on the pl061 model. This model implements all four banks with 32 I/Os
> each.
>
> The I/Os are placed in four named groups:
>
> * mio_in/out[0..63], where mio_in/out[0..31] map to bank 0 and the rest to
>bank 1
> * emio_in/out[0..
Based on the pl061 model. This model implements all four banks with 32 I/Os
each.
The I/Os are placed in four named groups:
* mio_in/out[0..63], where mio_in/out[0..31] map to bank 0 and the rest to
bank 1
* emio_in/out[0..63], where emio_in/out[0..31] map to bank 2 and the rest to
bank 3
