On 05/20/2011 12:34 AM, Max Filippov wrote:
> User registers represent TIE states that may appear in custom xtensa
> configurations. I'd better change RUR and WUR so that they can access
> all user registers but warn on those not defined globally or in the
> CPUEnv::config. Is it OK?
Well, it's ok
> > +enum {
> > +THREADPTR = 231,
> > +FCR = 232,
> > +FSR = 233,
> > +};
> > +
> > typedef struct XtensaConfig {
> > const char *name;
> > uint64_t options;
> > @@ -109,6 +115,7 @@ typedef struct CPUXtensaState {
> > uint32_t regs[16];
> > uint32_t pc;
> > uin
On 05/17/2011 03:32 PM, Max Filippov wrote:
> +enum {
> +THREADPTR = 231,
> +FCR = 232,
> +FSR = 233,
> +};
> +
> typedef struct XtensaConfig {
> const char *name;
> uint64_t options;
> @@ -109,6 +115,7 @@ typedef struct CPUXtensaState {
> uint32_t regs[16];
> uint3
Special Registers hold the majority of the state added to the processor
by the options. See ISA, 5.3 for details.
User Registers hold state added in support of designer's TIE and in some
cases of options that Tensilica provides. See ISA, 5.4 for details.
Only registers mapped in sregnames or ureg
